This invention relates to semiconductor devices and particularly to improved insulated-gate field effect transistor structures and method for producing said structures. More specifically the method includes within its accomplishments the accurate positioning of the gate electrode with respect to the source region and drain region, respectively, to provide improved performance of the field effect transistor. The improved performance is largely accomplished by a reduction in the parasitic capacitance.
Further, and significant to the improved performance of the field effect transistor the method provides field protection by subjecting the device at an appropriate stage during the construction of the device to bombardment by impurity ions of the same type as the background doping of the semiconductor body of the device. Field protection improves the performance of the device by materially reducing parasitic inversion and/or leakage current. Field protection also allows the use of more lightly doped substrate material which improves performance further by reducing parasitic junction capacitance.
The invention relates to transistor devices wherein the conductivity of a relatively shallow region in a semiconductor body is modulated by means of an electric field.
Operation of transistors of the insulated gate field effect type is based upon the control of a conduction channel in a semiconductor body. The channel is induced by an electric field established within the semiconductor body by an insulated control gate as well as by surface charges which may be ionic in nature. The transistors of the present invention are usually formed by deposition diffusion and/or ion implantation techniques. In transistors of the type to which the present invention is particularly directed, majority charge carriers (electrons or holes) flow through the solid state semiconductor material from an electrode usually called the "source". The conductive path for these charge carriers, hereinafter called the "channel" is modulated by an electric field and surface charges, and occurs at surface and near surface regions of the semiconductor body. In the absence of this induced channel, the flow of such charge carriers cannot occur. The charge carriers move or flow in the induced channel toward a second electrode called the "drain". The field effect in the semiconductor is established by a control or "gate" electrode and by this gate the conductivity of the channel and hence the majority charge carrier current reaching the drain can be varied. This control electrode or gate is insulated from the semiconductor material to prevent the majority carriers from flowing to it. Normally, these devices are operated in a drain-voltage region where the drain current saturates, or reaches a maximum, nearly constant value because the channel is pinched off or terminated very close to the drain region and acts as a current generator, the current being only a function of the gate voltage and not of the drain voltage. Thus, these devices basically exhibit the useful drain voltage-drain current characteristic similar to a vacuum pentode.
Such devices are well-known in the art and the structure and operation thereof have been fully described in numerous publications. In one arrangement, the field-effect transistors have the source and drain electrodes disposed side by side with the gate arranged over the space between the source and drain and separated therefrom by an insulator. The gate electrode is insulated from the semiconductor material so that the gate electrode will not itself act as a source or drain electrode. The gate electrode exerts its control by field effect in the space between the source and drain electrodes.
It is recognized by the art that it is highly desirable to precisely position the gate electrode over the channel region between the source and drain regions of the device. This permits the channel region between the source and drain to be completely modulated by the gate. If the gate is too wide relative to the channel region, undesirable and excessive stray capacitance is developed which reduces the frequency response of the device. If the gate is too small relative to the channel region and does not cover it in its entirety, undersirable ohmic losses are introduced into the device and low transconductance may result or the device may not function. The mask alignment problems involved in prior devices having a small channel region are severe since an extremely narrow gate must be precisely fitted over the channel region. Often in such prior art devices some compromise was accepted and the gate electrode was intentionally permitted to overlap the drain region in order to relieve the mask alignment problem. As noted, this results in the introduction of an undesirable capacitance usually referred to as Miller feedback capacitance.
During operation of integrated circuit devices utilizing F.E.T.s voltages exist and currents are conducted within the interconnection layers between the devices. The interconnection system consisting of one or more metallurgy stripes is separated from the semiconductor body by a relatively thick layer of field insulation. The voltages and currents in the interconnection system cause electrical fields and charges to build up in, on, and about the surface of the substrate and the overlying protective field insulation layer, which in turn gives rise to unwanted parasitic conduction paths along and near the device surface. Parasitic inversion of the field region of field effect transistors in integrated circuit devices is a common and serious problem, particularly in N channel type devices, and leads to current leakage. When parasitic conduction paths are allowed to extend from one active device to another, unwanted shorts and even catastrophic failures result. To control parasitic inversion, various methods are known in the art to control and prevent unwanted inversion. One technique is to provide special regions of increased conductivity to selected locations within the substrate in order to interrupt the inversion paths. These regions, usually formed by diffusion, are known as channel stops and are of the same conductivity as the substrate but with a higher surface concentration. Although satisfactory for some applications, the channel stop regions take up a relatively large portion of the available surface area thereby imposing serious restraints on the degree of miniaturization that can be achieved. For high density integrated circuits or complex arrays in which many field effect transistors are fabricated together in a small area on the substrate, the channel stop solution is unsatisfactory. Since parasitic inversion of the substrate surface is in general inversely proportioned to insulating layer thickness, unwanted parasitic inversion can also be reduced by increasing the thickness of the insulating layer. However, it is frequently impractical to increase the protective layer thickness to the extent necessary to control parasitic inversion due to fabricating difficulties. For example, it is difficult to substratively etch a relatively thick layer to very small geometries. Also, thick protective layers may develop contamination problems causing the electrical characteristics of the device to drift over a period of time. Another technique that has been suggested for controlling inversion is to imbed conductive layers in the field dielectric beneath the interrconnection layers that are connected to the body of the device. This technique also has its limitations since it requires additional fabricating process steps demanding additional masking, etching and aligning steps which, in general, decrease the overall yield of the device.
Another technique which has been suggested is to increase the conductivity in the field regions by a diffusion or ion bombardment. The techniques known to the art for increasing the impurity concentration require additional masking and etching steps, as well as heating steps which cause device yield loss due to the probability of inherent misalignments and movement of the diffusions within the device.
A means for controlling unwanted inversion along the substrate surface of an F.E.T. device is therefore needed that does not reduce available surface area, does not interfere with subsequent processing steps, does not increase the oxide thickness above a practical limit, and does not increase the turn-on voltage. The method disclosed and claimed in this application includes means for fullfilling this need for field-protection in field effect transistors.
The illustrative embodiments of the invention are particularly directed to the manufacture of an improved Metal Oxide Semiconductor having Ehancement Mode and Depletion Mode characteristics. The desired characteristics of these devices are well known to those skilled in the art and need not be recited herein.
As stated earlier the characteristics of M.O.S. F.E.T. devices of the enhancement mode and depletion mode are well-known to those skilled in the art. The invention disclosed herein is primarily directed to reducing the stray capacitance within an F.E.T. device and eliminating the parasitic channels between FET devices contained within a single semiconductor body.
It is a primary objective of the invention to provide an improved field-effect transistor device.
It is a further object of the invention to provide an improved field-effect transistor device having low parasitic or stray capacitance.
It is a further object of the invention to provide an improved field-effect transistor device having reduced parasitic inversion.
It is a further object of the invention to provide an improved field-effect transistor in which the gate is precisely located over the channel region between the source and drain regions.
It is further an object of the invention to provide an improved field-effect transistor in which the gate electrode is precisely aligned horizontally and longitudinally with respect to the channel region.
It is a further object of the invention to provide an improved field-effect transistor in which the area of the device lying outside of the source, drain and channel regions is field protected.
It is further an object of the invention to provide an improved method for precisely locating the gate over the channel region.
It is a further object of the invention to provide an improved method for accomplishing field protection in field-effect transistor.
It is a further object of the invention to provide an improved field effect transistor of the enhancement mode type.
It is a further object of the invention to provide an improved field-effect transistor of the depletion mode type.
It is a further object of the invention to provide a large scale integrated semiconductor device having a plurality of improved enhancement mode field-effect transistors and/or plurality of improved depletion mode field-effect tarnsistors.
It is further an object of the invention to provide a large scale integrated semiconductor device having a plurality of improved emhancement mode field effect transistors interconnected with a plurality of improved depletion mode field effect transistors.
These and other objects of the invention are achieved by employing a common masking structure, and modification of portions of said common masking structure to define and drain region, source region, channel region, to precisely position the gate electrode over the channel region, and to define the areas subjected to field protect.